When a via plug is formed by a single damascene method and an interconnect is formed on the via plug by reactive ion etching (RIE), the via plug and the interconnect are formed in the following manner, for example. First, a via hole is formed in an inter layer dielectric, and a barrier metal layer and a plug material layer are successively formed in the via hole, thereby forming the via plug in the inter layer dielectric. Next, a barrier metal layer and an interconnect material layer are successively formed on the via plug and the inter layer dielectric, thereby forming the interconnect on the via plug and the inter layer dielectric.
However, if the via plug is reduced in size, the contact area between the plug material layer in the via plug and the barrier metal layer in the interconnect is reduced. In this case, if the barrier metal layer in the interconnect has a high specific resistance, the contact resistance between the via plug and the interconnect becomes high. This results in problems that an increase in power consumption and a signal delay are caused in the via plug and the interconnect.